Inverter topology

What it is (precise)

Start at one phase leg. A two-level bridge switches the AC terminal to DC+ or DC- and nothing else. A three-level leg adds N, the midpoint of a split DC link, as a third node the terminal can reach — that third level is where the name comes from.

Device counts follow: Semikron Danfoss puts a 2L leg at 4 semiconductors, an NPC leg at 10 (4 IGBTs, 4 free-wheeling diodes, 2 clamping diodes), a T-type or TNPC leg at 8 (4 IGBTs and 4 free-wheeling diodes, no clamping diodes at all), and an ANPC leg at 12. Infineon describes ANPC the same way — classical NPC with the two clamping diodes replaced by actively controlled switches. TI's three-phase list for string inverters and storage PCS adds flying capacitor as a fifth option.

The count is not the point; the blocking voltage each die has to survive is. In NPC and ANPC the devices can be rated below the full DC-link voltage, which is a major advantage Semikron claims for those two: lower blocking class, lower losses, higher efficiency, or the same class used to reach a higher DC link. The T-type does not get that.

Its outer switches must withstand the full DC-link voltage while the inner pair, which connects AC to neutral, blocks only half — one leg, two voltage classes, deliberately. Device technology is a separate lever again: TI notes that wide-bandgap parts such as SiC and GaN allow operation at higher switching frequencies, which shrinks the passives and lifts power density.

The second axis is architectural and independent of the first. A central PCS puts one large converter on a single DC bus per battery block. A string architecture breaks the same power into many smaller inverters and usually more than one DC bus; typical market sizes for those units cluster around 215-230 kW and 430-450 kW each — practitioner figures from current market practice rather than a standard or a single vendor datasheet.

Sungrow's PowerTitan 2.0 white paper describes that pattern directly — string PCSs pre-integrated with the batteries, BMS, thermal management and fire suppression inside a 20-foot container. A third axis, control mode, is separate again: grid-forming and grid-following are control philosophy, not circuit, and either can sit on any of these legs.

Why it matters in a real grid-scale project

The third level is a budget, not a gift. Semikron states the trade in both directions: to hit the same current THD as a two-level design you can lower the switching frequency, which lowers switching losses, or you can hold the switching frequency and take the lower THD instead. Either way the output sits closer to a sine, so grid power-quality requirements are easier to meet and the filtering effort drops — less copper, lower filter losses. Decide which side of that trade you are buying, because the efficiency headline and the THD headline usually come from two different operating points.

The bill is conduction loss and control complexity. In an NPC leg the number of switches in the active current path doubles against two-level, raising conduction losses; ANPC carries the same clamped path. The T-type splits it: the outer path behaves like a two-level leg with the same losses, while the inner path puts two lower-voltage devices in series — higher conduction, lower switching loss.

Control scales too — switching states go from 4 in two-level to 16 in NPC and TNPC, 64 in ANPC, each added IGBT brings a gate driver and auxiliary draw, and TI marks shutdown sequencing as critical for NPC and ANPC. ANPC pays some of it back in modulation freedom: its HF/LF variants run one stage at line frequency and the other at the switching frequency, so SiC can go in the high-frequency stage alone.

The architectural choice changes different things: failure granularity, maintenance access, DC cabling and where the converter lives. String vendors put it this way — with units spread over more than one DC bus, losing one inverter leaves the rest of that bus in service; Sungrow claims an 8% output loss on a PCS fault because the remaining 11 units stay online, which implies 12 PCS per container, against a central unit whose fault takes its block to zero.

Read that as a vendor white paper, not a measurement. Paralleling smaller units also right-sizes a plant in finer steps, pulls conversion in beside the racks so DC runs get short and numerous, and moves the converters inside the battery enclosure instead of a separate skid — at the cost of far more units to commission, monitor and keep in sync.

Typical values and standards

For NPC and ANPC, Semikron Danfoss ties maximum DC-link voltage to device class directly: 800 VDC on 650 V semiconductors, 1500 VDC on 1200 V, 2400 VDC on 1700 V. That is the quantitative reason three-level suits a 1500 V DC bus — an NPC or ANPC reaches the link on 1200 V devices.

Two-level does not get the ratio; a component distributor states that 1700 V modules are the industry-standard choice for 1500 V DC systems on voltage-margin grounds, and Semikron's own two-level table agrees. A T-type sits with the two-level camp on its vertical leg, which AN 17-003 lists at 1700 V for a 1500 V link, with only the horizontal leg dropping to 1200 V.

The reliability numbers follow the same halving. Semikron notes that three-level has gained attention specifically in high-DC-voltage applications, which are also the ones most exposed to cosmic-ray failures. At 1500 V a 3L die blocks at most 750 V, where the measured failure rate of its semiconductors falls below 1 FIT/cm², so it calls 3L NPC modules effectively immune to cosmic-ray failures in contrast to their 2L counterparts.

The worked comparison is blunt: 230 FIT per switch for a 2L 1200 V module at 1000 V, against below the roughly 1 FIT measurement limit for a 3L part at 500 V blocking. Even a TNPC design lands near a third of the two-level rate, 80 FIT down to about 27 FIT in Semikron's example.

On standards, the scope boundary matters more than any topology clause. IEC 62477-1:2022 (Edition 2.0) covers power electronic converter systems, their accessories and components, including the means for control, protection, monitoring and measurement, at rated system voltages not exceeding 1000 V AC or 1500 V DC; above that boundary IEC 62477-2:2018 takes over, running to 36 kV AC or 54 kV DC.

That is why 1500 V DC is the top of the LV-classified band a grid-scale PCS is normally certified in. As of mid-2026, no IEC or IEEE standard consulted here prescribes or recommends a converter topology — they set safety and performance, and the circuit stays the vendor's choice.

How it shows up in specs, studies and contracts

Start with what the datasheet does not say. SMA's Sunny Central Storage 1900-2900 sheet names no IGBT, no MOSFET, no SiC and no topology; it sells 98.6% maximum efficiency, 98.3-98.4% European efficiency, THD under 3% at nominal power and an 1100 V DC ceiling, with the minimum DC voltage differing by model (477/545/614/740 V), and it footnotes those efficiencies as measured without the internal power supply.

Power Electronics' 1500 V, 690 V AC, 4390 kVA-class FREEMAQ MULTI PCSK quotes 98.93% maximum and 98.65% Euro efficiency over a 976-1500 V DC range with THDi under 3% per IEEE 519, and marks those figures preliminary. SMA's newer UP-S is announced at over 99.2% and up to 4,600 kVA, explicitly on SiC MOSFETs. Ask for topology, device class and measurement boundary in writing.

Architecture shows up as unit count and DC bus count, and it is where efficiency claims get mixed together. Sungrow quotes round-trip efficiency of up to 92.5% for a 4-hour PowerTitan 2.0 system, and that number is defined by Sungrow as the battery modules plus the PCS — a system figure with a ceiling word in front of it, not a conversion efficiency.

Setting it beside a 98-99% PCS number is a category error. Write the round-trip efficiency boundary into the specification: which components are inside it, at what temperature, over what duration, measured where. Apply the same discipline to redundancy: an 8%-instead-of-100% loss claim belongs in a witnessed test, not in a brochure.

In studies, topology surfaces as filter design, harmonics and the AC connection architecture. The FREEMAQ MULTI PCSK sheet points straight at IEEE 519 for its current-distortion limit, and a peer-reviewed review of MV-connected BESS converters makes the structural point: if low-voltage switches are used in the DC/AC stage for two- or three-level topologies, a step-up transformer is required to reach the MV grid.

Cascaded H-bridge and modular multilevel converters are the multilevel alternatives — the same review credits CHB with low-voltage switches, modularity, fault tolerance, low switching frequency and high output voltage quality, and notes a transformerless trend using two-level with series switches and MMC, while its own conclusion still prefers two- and three-level plus a step-up transformer on simplicity grounds. Keep control mode on its own line, because grid-forming is not a topology.

Common pitfalls

Pitfall one: treating three-level as a guarantee of lower distortion. In the peer-reviewed comparison of MV BESS converters, the 3L topology showed higher current distortion than expected, and the authors attributed it to the low switching frequency generally adopted for that converter — the extra level had been spent on switching loss, not on THD.

Distortion is a function of topology, modulation and switching frequency together, so a THD number quoted without its switching frequency compares to nothing. Note also that TI's much-quoted topology table has five columns, not four: it rates flying-capacitor 3L highest on efficiency, smallest on magnetics and lowest on EMI, so ANPC is not the winner of TI's own comparison.

Pitfall two: carrying figures across families and across scales. 1200 V devices on a 1500 V link is standard practice for NPC and ANPC, and wrong for two-level and for a T-type's outer switches; a distributor article warning against 1200 V at 1500 V is right only for the two-level design it was written about.

Semikron's own notes disagree with each other on the TNPC table, so get the module-specific numbers for the exact part rather than reasoning from the family name. And Infineon's 65 kHz and 99.15% peak figures come from an 11 kW SiC ANPC design measured near half load in PFC mode, where full-load efficiency is 98.96% — do not move them to an MW-class PCS.

Pitfall three: collapsing the axes. Central versus string tells you nothing about what is inside the leg; a container full of string PCS may be two-level or three-level, and grid-forming capability is orthogonal to both. Two more worth naming.

As of mid-2026 the widely repeated claim that the T-type wins below some switching-frequency crossover and loses above it could not be traced to a primary source for this entry, so treat any specific crossover number as unverified until the vendor shows loss curves at your operating point. And there is no authoritative published figure for what an MW-class BESS PCS actually switches at — the nearest numbers are 2.5-8 kHz cited for solar inverters and 10 kHz as an illustrative ANPC high-frequency-stage example.